(1). Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes for forming self-aligned-polysilicon-gate field effect transistors with lightly doped drains.
(2). Description of Prior Art
It has been determined that hot carrier effects will cause unacceptable performance degradation in n-channel MOS field effect transistors(MOSFETs) built with singly diffused drain structures if their channel length is below about 2 microns. This degradation is due primarily to high electric fields occurring in the drain region which cause the formation of hole-electron pairs by impact ionization. To overcome this problem the lightly-doped-drain (LDD) structure is widely used. A discussion of hot carriers and the formation of the LDD structure may be found in Wolf, S., "Silicon Processing for the VLSI Era", Vol. 2, Lattice Press, Sunset Beach, Calif., (1990), p 348ff. FIG. 1 shows a cross section of the LDD structure. The MOSFET 18 is formed on wafer 20 by first forming a field oxide 22 which surrounds the device. The silicon oxide gate insulator 24 is then grown by thermal oxidation of the silicon surface and a gate electrode 26, usually of doped polysilicon is defined by photolithographic techniques. Using the gate electrode as a mask, an ion-implantation forms the lightly-doped region 28 aligned to the gate electrode. A layer of insulative material, typically silicon oxide, is next deposited by low-pressure-chemical-vapor-deposition (LPCVD). This layer is then etched by a unidirectional technique, typically reactive-ion-etching (RIE) whereby silicon oxide sidewalls 30 are formed along the edges of the polysilicon gate electrode. The width of the sidewalls 30 corresponds roughly to the original thickness of the insulative layer. A second ion-implant is then performed at a higher dose to form the main portions 32 of the source/drain regions of the device. Both implantation are perfectly self-aligned to the gate electrode an require no photolithographic steps. By having reduced doping in the region 28 immediately at the edge of the channel region, the doping gradient is less abrupt. This results in a lower electric field and consequently a reduction of hot carrier generation.
A function of the oxide sidewall 30 is to provide spacing around the gate electrode to locate the source/drain implant away from the edge of the gate. After the implant is completed, an inter level dielectric (ILD) layer is deposited over the structure and contact openings are made to access the elements of the MOSFET. The oxide sidewall 30 becomes part of that ILD layer.
Although the just described method for forming the LDD structure using a silicon oxide sidewall is the most commonly used and easiest understood, other variations have been purported wherein the sidewall is fashioned of different materials. Hodate et. al. U.S. Pat. No. 5,518,940 forms the sidewall spacer of photoresist. The photoresist is selectively electro-deposited on the top and sides of the polysilicon gate electrode by application of a voltage to the electrode while the substrate wafer is submersed in an electrolyte. The application is the manufacture of liquid crystal displays. Such electro-deposition procedures are not compatible with current integrated circuit manufacturing processes.
Hodate points out several disadvantages of the oxide sidewall formation process. One is the non-uniformity of RIE plasma over large substrate areas. Another is a dependence of the sidewall thickness on the thickness of the polysilicon gate electrode.
Beinglass U.S. Pat. No. 4,975,385 describes a method of forming an LDD structure by using spacers of polysilicon which are selectively deposited on the edges of the polysilicon gate electrode after the LDD implantation. Only the edges (sidewalls) of the polysilicon gates are exposed during this deposition and a specified LPCVD process is used to deposit only on these exposed sidewalls. After the deposition the second high dosage source/drain implantation is made. The polysilicon sidewalls are not subsequently removed and become part of the structure. They therefore are prone to participate as part of the gate electrode affecting the resultant channel.
Reactive ion etching of patterns in insulative layers such as silicon oxide with halocarbon gases is typically accompanied by the formation of polymer deposits along the walls of the openings. It is also widely believed that the ability to achieve anisotropic etching of these materials in chloro-fluorocarbon gas mixtures is the direct result of the formation of these polymers. The polymer layer protects the sidewalls from chemical reaction while the etch front is kept clear of the polymer by ion bombardment. Unidirectional etching is thereby accomplished.
When pattern etching is completed steps are taken to remove the polymeric deposits before proceeding, usually by wet chemical dissolution. The task of removing both polymer and residual photoresist is accomplished by a combination of oxygen plasma ashing and the use of stripper solutions. Park et. al. U.S. Pat. No. 5,451,291 discusses the formation of via openings over aluminum using such combinations.
The growth of polymer along the sidewalls of the opening being etched can be well controlled both by the selection of etchant gases as well as adjustment of the RIE parameters. Thus the final thickness of the polymer deposit on the sidewall can also be pre-determined.